Recently, as the tendency toward miniaturization, high functionalization, and capacity enlargement of electronic equipment has been expanding and the need for densification and high integration of the semiconductor package has rapidly increased, the size of semiconductor chips becoming larger and larger. In terms of improvement of integration degree, the stack package method for laminating chips in multi-stages has gradually increased.
With the recent development trend of semiconductor packaging, miniaturization, thinning, and high performance of the semiconductor have proceeded rapidly. In addition, for the purpose of capacity enlargement of a package, the thickness of the semiconductor wafer is becoming very thin to less than 100 μm so that more chips can be laminated in the same package. Recently, the thickness of the semiconductor wafer has become extremely thin to less than 20 μm.
Thus, when manufacturing a package wherein the thickness of the semiconductor chip and the interlayer adhesive film is 20 μm or less, thinning of the adhesive film is required, whereby conventional manufacturing companies have provided an adhesive film not including inorganic particles.
Looking at the manufacturing process of the package, a semiconductor chip is laminated and then is subjected to a gold wire bonding process in order to conduct electricity.
In this case, due to impacts applied to chips during the wire bonding process, the semiconductor chips are easily cracked or damaged, whereby there may be a problem in the electronic properties after package assembling.
Furthermore, with the thinning of chips, the amount of impact applied to chips during wire bonding is larger. In order to prevent this, an adhesive film which is attached to the semiconductor chips needs to have impact resistance with respect to an impact applied from the outside, thereby protecting the chips.